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Final Electrical Specifications
LTC1484 Low Power EIA485 Transceiver with Receiver Fail-Safe
September 1998
FEATURES
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DESCRIPTION
The LTC(R)1484 is a low power EIA485 compatible transceiver. In receiver mode, it offers a fail-safe feature which guarantees a high receiver output state when the inputs are left open, shorted together or terminated with no signal present. No external components are required to ensure the high receiver output state. Both driver and receiver feature three-state outputs with separate receiver and driver control pins. The driver outputs maintain high impedance over the entire common mode range when three-stated. Excessive power dissipation caused by bus contention or faults is prevented by a thermal shutdown circuit that forces the driver outputs into a high impedance state. Enhanced ESD protection allows the LTC1484 to withstand 15kV (human body model), IEC-1000-4-2 level 4 (8kV) contact and level 3 (8kV) air discharge ESD without latchup or damage. The LTC1484 is fully specified over the commercial and industrial temperature ranges and is available in 8-lead MSOP, PDIP and SO packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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No Damage or Latchup to 15kV ESD (Human Body Model), IEC-1000-4-2 Level 4 Contact (8kV) and Level 3 (8kV) Air Gap Specifications Guaranteed High Receiver Output State for Floating, Shorted or Terminated Inputs with No Signal Present Drives Low Cost Residential Telephone Wires Low Power: ICC = 700A Max with Driver Disabled ICC = 900A Max for Driver Enable with No Load 20A Max Quiescent Current in Shutdown Mode Single 5V Supply - 7V to 12V Common Mode Range Permits 7V Ground Difference Between Devices on the Data Line Power Up/Down Glitch-Free Driver Outputs Up to 32 Transceivers on the Bus Pin Compatible with the LTC485 Available in 8-Lead MSOP, PDIP and SO Packages
APPLICATIONS
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Battery-Powered EIA485/EIA422 Applications Low Power EIA485/EIA422 Transceiver Level Translator
TYPICAL APPLICATION
EIA485 Interface
RO1 RE DE1 D DI1 R B A
VCC1 120 GND1
VCC2 B 120 GND2
1484 TA01
R
A D
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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RO2 RE DE2 DI2
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LTC1484
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Supply Voltage (VCC)............................................... 6.5V Control Input Voltages ................. - 0.3V to (VCC + 0.3V) Driver Input Voltage ..................... - 0.3V to (VCC + 0.3V) Driver Output Voltages ................................. - 7V to 10V Receiver Input Voltages (Driver Disabled) .. -12V to 14V Receiver Output Voltage ............... - 0.3V to (VCC + 0.3V)
PACKAGE/ORDER INFORMATION
ORDER PART NUMBER
TOP VIEW RO RE DE DI 1 2 3 4 8 7 6 5 VCC B A GND
TOP VIEW RO 1 RE 2 DE 3 D DI 4 R 8 7 6 5 VCC B A GND
LTC1484CMS8
MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125C, JA = 200C/ W
MS8 PART MARKING LTDX
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL VOD1 VOD2 PARAMETER Differential Driver Output Voltage (Unloaded) Differential Driver Output Voltage (with Load)
VCC = 5V 5% (Notes 2 and 3) unless otherwise noted.
CONDITIONS IOUT = 0 R = 50 (RS422) R = 27 (RS485) Figure 1 R = 22, Figure 1 VTST = - 7V to 12V, Figure 2 R = 22, 27 or R = 50, Figure 1 VTST = - 7V to 12V, Figure 2 R = 22, 27 or R = 50, Figure 1 R = 22, 27 or R = 50, Figure 1 DE, DI, RE DE, DI, RE DE, DI, RE DE = 0, VCC = 0 or 5V, VIN = 12V DE = 0, VCC = 0 or 5V, VIN = - 7V - 7V VCM 12V, DE = 0
q q q q q q q q q q q q q
VOD3 VOD VOC |VOC| VIH VIL IIN1 IIN2 VTH
Differential Driver Output Voltage (with Common Mode) Change in Magnitude of Driver Differential Output Voltage for Complementary Output States Driver Common Mode Output Voltage Change in Magnitude of Driver Common Mode Output Voltage for Complementary Output States Input High Voltage Input Low Voltage Input Current Input Current (A, B) Differential Input Threshold Voltage for Receiver
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Junction Temperature .......................................... 125C Operating Temperature Range LTC1484C.......................................... 0C TA 70C LTC1484I ...................................... - 40C TA 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1484CN8 LTC1484CS8 LTC1484IN8 LTC1484IS8 S8 PART MARKING 1484 1484I
N8 PACKAGE 8-LEAD PDIP
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 125C, JA = 130C/ W (N8) TJMAX = 125C, JA = 135C/ W (S8)
MIN 2 1.5 1.5
TYP
MAX VCC 5 5 0.2 3 0.2
UNITS V V V V V V V V V
2.0 0.8 2 1.0 - 0.8 - 0.20 - 0.015
V A mA mA V
LTC1484
ELECTRICAL CHARACTERISTICS
SYMBOL VTH VOH VOL IOZR RIN ICC ISHDN IOSD1 IOSD2 IOSR PARAMETER Receiver Input Hysteresis Receiver Output High Voltage Receiver Output Low Voltage Three-State (High Impedance) Output Current at Receiver Receiver Input Resistance Supply Current Supply Current in Shutdown Mode Driver Short-Circuit Current, VOUT = High (Note 4) Driver Short-Circuit Current, VOUT = Low (Note 4) Receiver Short-Circuit Current
VCC = 5V 5% (Notes 2 and 3) unless otherwise noted.
CONDITIONS VCM = 0V, DE = 0 IOUT = - 4mA, (VA - VB) = 200mV IOUT = 4mA, (VA - VB) = - 200mV VCC = Max, 0.4V VOUT 2.4V, DE = 0 -7V VCM 12V No Load, Output Enabled (DE = VCC) No Load, Output Disabled (DE = 0) DE = 0, RE = VCC, DI = 0 - 7V VOUT 10V - 7V VOUT 10V 0V VOUT VCC
q q q q q q q q q
MIN 3.5
TYP 30
MAX
UNITS mV V
0.4 1 12 22 600 400 10 35 35 7 900 700 20 250 250 85
V A k A A A mA mA mA
SWITCHING CHARACTERISTICS
SYMBOL tPLH tPHL tSKEW tr, tf tZH tZL tLZ tHZ tPLH tPHL tSKD tZL tZH tLZ tHZ tDZR fMAX tSHDN PARAMETER Driver Input to Output Driver Input to Output Driver Output to Output Driver Rise or Fall Time Driver Enable to Output High Driver Enable to Output Low Driver Disable Time from Low Driver Disable Time from High Receiver Input to Output Receiver Input to Output |tPLH - tPHL| Differential Receiver Skew Receiver Enable to Output Low Receiver Enable to Output High Receiver Disable from Low Receiver Disable from High Driver Enable to Receiver Valid Maximum Data Rate (Note 5) Time to Shutdown (Note 6) DE = 0, RE CONDITIONS RDIFF = 54, CL1 = CL2 = 100pF (Figures 4, 6) RDIFF = 54, CL1 = CL2 = 100pF (Figures 4, 6) RDIFF = 54, CL1 = CL2 = 100pF (Figures 4, 6) RDIFF = 54, CL1 = CL2 = 100pF (Figures 4, 6) CL = 100pF (Figures 5, 7) S2 Closed CL = 100pF (Figures 5, 7) S1 Closed CL = 15pF (Figures 5, 7) S1 Closed CL = 15pF (Figures 5, 7) S2 Closed RDIFF = 54, CL1 = CL2 = 100pF, (Figures 4, 8) RDIFF = 54, CL1 = CL2 = 100pF, (Figures 4, 8) RDIFF = 54, CL1 = CL2 = 100pF, (Figures 4, 8) CRL = 15pF (Figures 3, 9) S1 Closed CRL = 15pF (Figures 3, 9) S2 Closed CRL = 15pF (Figures 3, 9) S1 Closed CRL = 15pF (Figures 3, 9) S2 Closed RDIFF = 54, CL1 = CL2 = 100pF (Figures 4, 10)
q q q q q q q q q q q q q q q q q
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MIN 10 10
TYP 25 25 5
MAX 60 60 10 40 70 100 70 70 200 200
UNITS ns ns ns ns ns ns ns ns ns ns ns
3
15 40 40 40 40
30 30
140 140 5 20 20 20 20 1600
50 50 50 50 3000
ns ns ns ns ns Mbps
4 50
5 300 600
ns
3
LTC1484
SWITCHING CHARACTERISTICS
SYMBOL tZH(SHDN) tZL(SHDN) tZH(SHDN) tZL(SHDN) PARAMETER Driver Enable from Shutdown to Output High Driver Enable from Shutdown to Output Low Receiver Enable from Shutdown to Output High Receiver Enable from Shutdown to Output Low
The q denotes specifications which apply over the full specified temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All typicals are given for VCC = 5V and TA = 25C. Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified.
PIN FUNCTIONS
RO (Pin 1): Receiver Output. If the receiver output is enabled (RE low) and the part is not in shutdown, RO is high if (A - B) > VTH(MAX) and low if (A - B) < VTH(MIN). RO is also high if the receiver inputs are open or shorted together, with or without a termination resistor. RE (Pin 2): Receiver Output Enabled. A high on this pin three-states the receiver output (RO) and a low enables it. DE (Pin 3): Driver Enable Input. DE = high enables the output of the driver with the driver outputs determined by the DI pin. DE = low forces the driver outputs into a high impedance state. The LTC1484 enters shutdown when both receiver and driver outputs are disabled (RE is high and DE is low). DI (Pin 4): Driver Input. When the driver outputs are enabled (DE high), DI high takes the A output high and the B output low. DI low takes the A output low and the B output high. GND (Pin 5): Ground. A (Pin 6): Driver Output/Receiver Input. The input resistance is typically 22k when the driver is disabled (DE = 0). When the driver is enabled, the A output follows the logic level at the DI pin. B (Pin 7): Driver Output/Receiver Input. The input resistance is typically 22k when the driver is disabled (DE = 0). When the driver is enabled, the B output is inverted from the logic level at the DI pin. VCC (Pin 8): Positive Supply. 4.75V VCC 5.25V. A 0.1F bypass capacitor is recommended.
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VCC = 5V 5% (Notes 2 and 3) unless otherwise noted.
CONDITIONS CL = 100pF (Figures 5, 7) S2 Closed, DI = DE CL = 100pF (Figures 5, 7) S1 Closed, DI = 0 CL = 15pF (Figures 3, 9) S2 Closed, DE = 0 CL = 15pF (Figures 3, 9) S1 Closed, DE = 0
q q q q
MIN
TYP 40 40
MAX 100 100 10 10
UNITS ns ns s s
Note 4: For higher ambient temperatures, the part may enter thermal shutdown during short-circuit conditions. Note 5: Guaranteed by design. Note 6: Time for ICC to drop to ICC/2 when the receiver is disabled.
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LTC1484
FU CTIO TABLES
Driver
INPUTS RE X X O 1 DE 1 1 0 0 DI 1 0 X X B 0 1 Z Z* OUTPUTS A 1 0 Z Z* RE 0 0 0 0 1 DE 0 0 0 0 X
Note: Z = high impedance, X = don't care *Shutdown mode for LTC1484
TEST CIRCUITS
375
A R VOD1 VOD2 R B
1484 F01
Figure 1
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Receiver
INPUTS A-B VTH(MAX) VTH(MIN) Inputs Open Inputs Shorted X OUTPUTS RO 1 0 1 1 Z
Shutdown mode for LTC1484 if DE = 0. Table valid with or without
termination resistors.
A
VOD3
VOC
60 375
OUTPUT UNDER TEST
-7V TO 12V
S1
1k VCC
CRL
1k
S2
1484 F03
B
1484 F02
Figure 2
Figure 3
DE A DI B A RO B CL2 RE
1484 F04
CL1
15pF
Figure 4
S1 OUTPUT UNDER TEST 500 CL S2
1484 F05
VCC
Figure 5
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LTC1484
SWITCHI G TI E WAVEFOR S
3V DI 0V t PLH VO -VO B VO A 1/2 VO NOTE: DE = 1 tSKEW t SKEW
1484 F06
1.5V
10% tr
90% 50%
Figure 6. Driver Propagation Delays
3V DE 0V 5V A, B VOL VOH A, B 0V t ZH(SHDN), t ZH 2.3V t ZL(SHDN), t ZL 2.3V 1.5V
NOTE: A, B ARE THREE-STATED WHEN DE = 0, 1k PULL-UP OR 1k PULL-DOWN
Figure 7. Driver Enable and Disable Timing
VOD2 A-B - VOD2 5V RO VOL
0V t PHL 1.5V NOTE: tSKD = |tPHL - tPLH|, RE = 0
Figure 8. Receiver Propagation Delays
RE
1.5V t ZL(SHDN), tZL 1.5V 0V 5V
5V RO
RO 0V
1.5V t ZH(SHDN), tZH
NOTE: DE = 0, RO IS THREE-STATED IN SHUTDOWN, 1k PULL-UP FOR NORMALLY LOW OUTPUT, 1k PULL-DOWN FOR NORMALLY HIGH OUTPUT
Figure 9. Receiver Enable and Shutdown Timing
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f = 1MHz, tr 10ns, tf 10ns t PHL VO = V(A) - V(B) 50% tf
1.5V
90% 10%
f = 1MHz, tr 10ns, tf 10ns t LZ OUTPUT NORMALLY LOW
1.5V
0.5V 0.5V t HZ
1484 F07
OUTPUT NORMALLY HIGH
INPUT f = 1MHz, tr 10ns, tf 10ns OUTPUT t PLH
0V
1.5V
1484 F08
f = 1MHz, tr 10ns, tf 10ns t LZ OUTPUT NORMALLY LOW
1.5V
0.5V 0.5V t HZ
1484 F09
OUTPUT NORMALLY HIGH
LTC1484
SWITCHI G TI E WAVEFOR S
3V DE 0V t DZR V(A) - V(B) OUTPUT NORMALLY LOW 1.5V f = 1MHz, tr 10ns, tf 10ns
RO
1.5V
NOTE: DI = 0, RE = 0, A AND B ARE THREE-STATED WHEN DE = 0
Figure 10. Driver Enable to Receiver Valid Timing
APPLICATIONS INFORMATION
Low Power Operation The LTC1484 has a quiescent current of 900A max when the driver is enabled. With the driver in three-state, the supply current drops to 700A max. The difference in these supply currents is due to the additional current drawn by the internal 22k receiver input resistors when the driver is enabled. Under normal operating conditions, the additional current is overshadowed by the 50mA current drawn by the external termination resistor. Receiver Open-Circuit Fail-Safe Some encoding schemes require that the output of the receiver maintain a known state (usually a logic 1) when data transmission ends and all drivers on the line are forced into three-state. Earlier EIA485 receivers with a weak pull-up at the A input will give a high output only when the inputs are floated. When terminated or shorted together, the weak pull-up is easily defeated causing the receiver output to go low. External components are needed if a high receiver output is mandatory. The receiver of the LTC1484 has a fail-safe feature which guarantees the output to be in a logic 1 when the receiver inputs are left open or shorted together, regardless of whether the termination resistor is present or not. In encoding schemes where the required known state is a low, external components are needed for the LTC1484 and other EIA485 parts. Fail-safe is achieved by making the receiver trip points fall within the VTH(MIN) to VTH(MAX) range. When any of the listed receiver input conditions exist, the receiver inputs are effectively at 0V and the receiver output goes high. The receiver fail-safe mechanism is designed to reject fast common mode steps (- 7V to 12V in 10ns) switching at 100kHz typ. This is achieved through an internal carrier detect circuit similar to the LTC1482. This circuit has builtin delays to prevent glitches while the input swings between VTH(MAX) levels. When all the drivers connected to the receiver inputs are three-stated, the internal carrier detect signal goes low to indicate that no differential signal is present. When any driver is taken out of three-state, the carrier detect signal takes 1.6s typ (see tDZR) to detect the enabled driver. During this interval, the transceiver output (RO) is forced to the fail-safe high state. After 1.6s, the receiver will respond normally to changes in driver output. If the part is taken out of shutdown mode with the receiver inputs floating, the receiver output takes about 10s to leave three-state. If the receiver inputs are actively driven to a high state, the outputs go high after about 5.5s (see tZL(SHDN)).
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OUTPUT NORMALLY HIGH
1484 F10
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LTC1484
APPLICATIONS INFORMATION
Shutdown Mode The receiver output (RO) and the driver outputs (A, B) can be three-stated by taking the RE and DE pins high and low respectively. Taking RE high and DE low at the same time puts the LTC1484 into shutdown mode and ICC drops to 20A max. In some applications (see CDMA), the A and B lines are pulled to VCC or GND through external resistors to force the line to a high or low state when all connected drivers are disabled. In shutdown, the supply current will be higher than 20A due to the additional current drawn through the external pull-up and the 22k input resistance of the LTC1484. ESD Protection The ESD performance of the LTC1484 A and B pins is characterized to meet 15kV using the Human Body Model (100pF, 1.5k), IEC-1000-4-2 level (8kV) contact mode and IEC-1000-4-2 level 3 (8kV) air discharge mode. This means that external voltage suppressors are not required in many applications when compared with parts that are only protected to 2kV. Pins other than the A and B pins are protected to 4.5kV typical per the Human Body Model. When powered up, the LTC1484 does not latch up or sustain damage when the A and B pins are tested using any of the three conditions listed. The data during the ESD event may be corrupted, but after the event the LTC1484 continues to operate normally. The additional ESD protection at the A and B pins is important in applications where these pins are exposed to the external world via connections to sockets. Fault Protection When shorted to -7V or 10V at room temperature, the short-circuit current in the driver pins is limited by internal resistance or protection circuitry to 250mA. Over the industrial temperature range, the absolute maximum positive voltage at any driver pin should be limited to 10V to avoid damage to the driver pins. At higher ambient temperatures, the rise in die temperature due to the short-circuit current may trip the thermal shutdown circuit. When the driver is disabled, the receiver inputs can withstand the entire - 7V to 12V EIA485 common mode range without damage. The LTC1484 includes a thermal shutdown circuit which protects the part against prolonged shorts at the driver outputs. If a driver output is shorted to another output or to VCC, the current will be limited to 250mA. If the die temperature rises above 150C, the thermal shutdown circuit three-states the driver outputs to open the current path. When the die cools down to about 130C, the driver outputs are taken out of three-state. If the short persists, the part will heat again and the cycle will repeat. This thermal oscillation occurs at about 10Hz and protects the part from excessive power dissipation. The average fault current drops as the driver cycles between active and three-state. When the short is removed, the part will return to normal operation. Carrier Detect Multiple Access (CDMA) Application In normal half-duplex EIA485 systems, only one node can transmit at a time. If an idle node suddenly needs to gain access to the twisted pair whilst other communications are in progress, it must wait its turn. This delay is unacceptable in safety-related applications. A scheme known as Carrier Detect Multiple Access (CDMA) solves this problem by allowing any node to interrupt on-going communications. Figure 11 shows four nodes in a typical CDMA communications system. In the absence of any active drivers, bias resistors (1.2k) force a "1" across the twisted pair. All drivers in the system are connected so that when enabled, they transmit a "0". This is accomplished by tying DI low and using DE as the driver data input. A "1" is transmitted by disabling the driver's "0" output and allowing the bias resistors to reestablish a "1" on the twisted pair. Control over communications is achieved by asserting a "0" during the time an active transmitter is sending a "1". Any node that is transmitting data watches its own
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LTC1484
APPLICATIONS INFORMATION
1k RO4 DE4 123 5V 1.2k 5V 8 67 120 67 76 R 4 D 5 5 76 120 D 4 DE2 RO2 321 R 8 5V 5V 1.2k 1k
1.2k
5V
8 R 1 1k
5
D 23 4
RO1 DE1
Figure 11. Transmit "0" CDMA Application
receiver output and expects to see perfect agreement between the two data streams. (Note that the driver inverts the data, so the transmitted and received data streams are actually opposites.) If the simultaneously transmitted and received data streams differ (usually detected by comparing RO and DE with an XOR), it signals the presence of a second, active driver. The first driver falls silent, and the second driver seizes control. If the LTC1484 is connected as shown in Figure 11, the overhead of XORing the transmitted and received data in hardware or software is eliminated. DE and RE are connected together so the receiver is disabled and its output three-stated whenever a "0" is transmitted. A 1k pull-up ensures a "1" at the receiver output during this condition. The receiver is enabled when the driver is disabled. During this interval the receiver output should also be "1". Thus, under normal operation the receiver output is always "1". If a "0" is detected, it indicates the presence of a second active driver attempting to seize control of communications. The maximum frequency at which the system in Figure 11 can operate is determined by the cable capacitance, the value of the 1.2k pull-up and pull-down resistors and receiver propagation delay. The external resistors take a longer time to pull the line to a "1" state due to higher source resistance compared to an active driver, thereby affecting the duty cycle of the receiver output at the far end of the line.
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5
8
5V
1.2k
D 4
R 321
1484 F11
DE3 RO3
1k
Figure 12a shows a 100kHz DE1 waveform for an LTC1484 driving a 1000-foot shielded twisted-pair (STP) cable and the A2, B2 and RO2 waveforms of a receiving LTC1484 at the far end of the cable. The propagation delay between DE1 of the driver and RO2 at the far end of the line is 1.8s at the rising edge and 3.7s at the falling edge of DE1. The
DE1
B2 A2
RO2
A
1484 F12a
DE1
B2
A2 RO2
B
1484 F12b
Figure 12. LTC1484 Driving a 1000 Foot STP Cable
9
LTC1484
APPLICATIONS INFORMATION
longer delay for the falling edge is due to the larger voltage range the line must swing (typically > 2V compared to 370mV) before the receiver trips high again. The difference in delay affects the duty cycle of the received data and depends on cable capacitance. For a 1-foot STP cable, the delays drop to 0.13s and 0.4s. Using smaller valued pull-up and pull-down resistors to equalize the positive and negative voltage swings needed to trip the receivers will reduce the difference in delay and increase the maximum data rate. With 220 resistors, both rising and falling edge delays are 2.2s when driving a 1000-foot STP cable as shown in Figure 12b. The fail-safe feature of the LTC1484 receiver allows a CDMA system to function without the A and B pull-up and pull-down resistors. However, if the resistors are left out, noise margin will be reduced to as low as 15mV and propagation delays will increase significantly. Operation in this mode is not recommended. Since DE and RE are tied together, the part never shuts down. The receiver inputs are never floating (due to the external bias resistors) so that the tDZR timing does not apply to this application. The whole system can be changed to actively transmit only a "1" by swapping the pull-up and pull-down resistors in Figure 11, shorting DI to VCC and connecting the 1k resistor as a pull-down. In this configuration the driver is noninverting and the receiver output RO truly follows DE.
PACKAGE DESCRIPTION
Dimensions in inches (millimeters), unless otherwise noted.
0.007 (0.18) 0.021 0.006 (0.53 0.015)
0 - 6 TYP SEATING PLANE 0.012 (0.30) 0.0256 REF (0.65) TYP
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
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MS8 Package 8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 0.004* (3.00 0.102) 8 76 5
0.192 0.004 (4.88 0.10)
0.118 0.004** (3.00 0.102)
1 0.040 0.006 (1.02 0.15)
23
4 0.034 0.004 (0.86 0.102)
0.006 0.004 (0.15 0.102)
MSOP (MS8) 1197
LTC1484
PACKAGE DESCRIPTION
0.300 - 0.325 (7.620 - 8.255)
0.009 - 0.015 (0.229 - 0.381)
(
+0.035 0.325 -0.015 8.255 +0.889 -0.381
)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
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Dimensions in inches (millimeters), unless otherwise noted.
N8 Package 8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400* (10.160) MAX 8 7 6 5
0.255 0.015* (6.477 0.381)
1
2
3
4 0.130 0.005 (3.302 0.127)
0.045 - 0.065 (1.143 - 1.651)
0.065 (1.651) TYP 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 0.003 (0.457 0.076) N8 1197
0.100 0.010 (2.540 0.254)
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LTC1484
PACKAGE DESCRIPTION
0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0- 8 TYP
0.016 - 0.050 0.406 - 1.270
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RELATED PARTS
PART NUMBER LTC485 LTC1480 LTC1481 LTC1482 LTC1483 LTC1485 LTC1487 LTC1690 DESCRIPTION 5V Low Power EIA485 Interface Transceiver 3.3V Ultralow Power EIA485 Transceiver with Shutdown 5V Ultralow Power EIA485 Transceiver with Shutdown 5V Low Power EIA485 Transceiver with Carrier Detect Output 5V Ultralow Power EIA485 Low EMI Transceiver with Shutdown 5V Differential Bus Transceiver 5V Ultralow Power EIA485 with Low EMI, Shutdown and High Input Impedance 5V Differential Driver and Receiver Pair with Fail-Safe Receiver Output COMMENTS Low Power Lower Supply Voltage Lowest Power Low Power, High Output State When Inputs are Open, Shorted or Terminated Low EMI, Lowest Power Highest Speed Highest Input Impedance, Low EMI, Lowest Power Low Power
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
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Dimensions in inches (millimeters), unless otherwise noted.
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 - 0.197* (4.801 - 5.004) 8 7 6 5
0.228 - 0.244 (5.791 - 6.197)
0.150 - 0.157** (3.810 - 3.988)
1 0.053 - 0.069 (1.346 - 1.752)
2
3
4
0.004 - 0.010 (0.101 - 0.254)
0.014 - 0.019 (0.355 - 0.483)
0.050 (1.270) TYP
SO8 0996
1484i LT/TP 0998 4K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1998

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